
module RxV32_main (
    data_in,
    data_out,
    data_cs,
    data_dir,
    clk,
    cpu_run,
    led,
    sys_clk,
    xdata,
);
    input wire data_in;
    output wire data_out; reg data_outr = 'b1; assign data_out = data_outr;
    input wire data_cs;
    input wire data_dir;
    input wire clk;
    input wire cpu_run;
    output reg [2:0] led = 3'b110;
    input wire sys_clk;
    output reg xdata = 'b0;
    reg [7:0] counter;

//    always @(posedge sys_clk) begin
//        if (counter == 24'd1200_0000)       // 0.5s delay
//            led[2:0] <= {led[1:0],led[2]};
//        else
//            led <= led;
//    end

//    always @(posedge sys_clk) begin
//        if (counter < 24'd1200_0000)       // 0.5s delay
//            counter <= counter + 1;
//        else
//            counter <= 24'd0;
//    end
    always @(posedge sys_clk)begin
        if((addr_out=='h400)&rv_data_w)begin
            //xdata <= dout_o[0];
        end
        if(data_cs)begin
            counter <= counter + 1;
        end
    end
    always @(posedge rv_data_w) begin
        if((addr_out=='h400))begin
            xdata <= rv_data_out[0];
        end
    end

    reg [4:0] data_bit_pos = 'd0;
    reg [31:0] data_r = 'd0;
    reg [7:0] data_pos = 'd0;
    reg w_start = 'b0;

    reg wre_i = 'b0;
    wire [31:0] dout_o;
    wire [31:0] di_i; assign di_i = data_r;
    wire [7:0] ad_i; assign ad_i = data_pos[7:0];
    wire [31:0] rv_addr_out;
    wire [31:0] addr_out;
    wire rv_data_w;
    wire[31:0] rv_data_out;

   RxV32a rv32(
       .clk_in   (clk&data_cs),
       //.clk_in   (($unsigned(counter)>'h80)&data_cs),
       .cpu_run  (cpu_run),
       .addr_out (addr_out),
       .data_in  (dout_o),
       .data_out (rv_data_out),
       .data_w   (rv_data_w),
       .rst_n    ('b0),
       .rv_reg   (data_pos[4:0])
   );

    Gowin_SP GO_SP(
        .dout(dout_o), //output [31:0] dout
        .clk(~clk),
        //.clk(~counter[2]), //input clk  看时序图需要取反,更新数据
        .oce('b1), //input oce
        .ce('b1), //input ce
        .reset('b0), //input reset
        .wre(data_cs?(rv_data_w&!addr_out[10]):wre_i), //input wre
        .ad(cpu_run?addr_out[10:2]:ad_i), //input [7:0] ad
        .din(data_cs?rv_data_out:di_i) //input [31:0] din
    );

    always @(posedge clk) begin
        if(!data_cs)begin
            if(data_dir)begin
                //先把数据写入sram
                data_r[data_bit_pos] <= data_in;
                if((data_bit_pos=='h1f))begin
                    //31时 写入数据
                    data_pos <= data_pos + w_start;
                    wre_i <= 'b1;
                    w_start <= 'b1;
                end
                else begin
                    //关闭写入
                    wre_i <= 'b0;
                end
                data_bit_pos <= data_bit_pos + 1;
            end
            else begin
                wre_i <= 'b0;
                if(data_pos>='h40)begin
                    data_outr <= rv_data_out[data_bit_pos];
                end
                else begin
                    data_outr <= dout_o[data_bit_pos];
                end
                //读取sram数据
                if(data_bit_pos=='h1f)begin
                    data_pos <= data_pos + 1;
                end
                data_bit_pos <= data_bit_pos + 1;
            end
        end
        else begin
            w_start <= 'b0;
            wre_i <= 'b0;
            data_pos <= 'd0;
            data_bit_pos <= 'd0;
        end
    end
endmodule